1) Perform analog/mixed signal layout for short range RF wireless applications (i.e. WiFi, BT etc.) using advanced sub-micron CMOS/SiGe/GaAs technologies.
2) Configure foundry DRC/LVS rules and perform physical verifications on completed RFIC layout such as DRC, LVS, ERC, Antenna, Density, ESD, LUP, EM, IR, etc.
3) Run layout parasitic extraction in preparation for postlayout simulation and optimization.
4) Integration of RFIC chip for tapeout to foundry.
1) More than 3 years RFIC layout and Top-level IC integration experience in CMOS (28nm, 16nm, 7nm, 5nm)/SiGe/GaAs process
2) Experience in layout of RF building blocks such as PA / LNA / Mixer / VCO / IF filter / Balun / Inductor etc.
3) Must have strong knowledge in RFIC layout verification flow (i.e DRC, ERC, LVS, ANT etc) and usage of CAD layout verification tools such as Cadence, Mentor Graphics tools.
4) Highly motivated, able to work independently and demonstrates strong troubleshooting and communication skills.
5) Some experience in script writing such as pearl, skill etc will be advantageous.
6) Good interpersonal and creative skills with the ability to multitask in a demanding and fast paced environment.
7) Pleasant character and good team player.