Packaging Engineer (Up to SGD$7,000)

Location: West Region
Job Type: Permanent
Reference: JO-1911-6783
  • Work life balance+MNC Company
  • Career Development Opportunities
  • Attractive Salary Package

Roles & Responsibilities:

  • Working with customer to provide 2.5D/3DIC competitive engineering solution for AI/CPU, Mobile, network chip, considering PPA, Electrical performance, yield, reliability, etc
  • Benchmarking and Pathfinding for 2.5D/3DIC technology development, including wafer process, C2W/W2W stack, Advanced packaging, etc

 

Requirements:

  • Preferably Master or PhD degree in material science and Semiconductor with over 10 years’ R&D experience
  • Extensive knowledge and experience in Wafer Process Integration, such as BEOL Integration, 2.5D/3D integration with TSV, etc
  • Extensive knowledge and experience in Package design and process, such as FcBGA, wafer level Fan-in & Fan-Out package, etc
  • Good knowledge in design and reliability, such as TV design, Si/PI, CPI, Thermo-mechanical analysis, DFR etc
  • Good communication and interpersonal skills